1. Field of the Invention
The present invention relates to a shift operation unit and a shift operation method. More specifically, the present invention relates to a shift operation unit and a shift operation method for executing multiple-precision shift operation by use of hardware for processing single-precision data.
2. Description of the Related Art
With recent rapid progress in the field of digital technology, processors capable of executing high-level processing such as digital signal processing are required. Some of such high-level processing requires high operational precision. For example, a short-term prediction analysis processing in a CELP (code excited linear prediction) type voice CODEC requires an operational precision of the order of 36 bits. The CELP type voice CODEC is one of the voice CODECs which are indispensable for digital sound communication. It is not advisable, however, to realize high operational precision by means of hardware, because, in order to obtain high operational precision, the circuitry of a processor needs to be large, and thus the cost and power consumption increase. In order to overcome this problem, techniques for realizing double-precision operation by combining a plurality of commands using hardware for processing single-precision data have been developed. The double-precision operation includes double-precision addition, double-precision subtraction, double-precision shift operation, and the like.
FIG. 9 shows a conventional shift operation unit for executing double-precision shift operation by use of hardware for processing 24-bit data. The shift operation unit includes registers 110 and 111, a shifter 120 for shifting 24-bit data (A) in accordance with the shift count stored in the registers 110 and 111, an arithmetic and logic unit (ALU) 160 for operating 24-bit data (E) and 24-bit data (D) output from the shifter 120, and 24-bit registers 170, 171, and 172 for storing the operation results of the ALU 160.
Hereinbelow,, a method for shifting double-precision data leftward by N bit(s) by use of the shift operation unit having the above-described configuration will be described (N is an integer equal to or more than 1). In the following description, the double-precision data is composed of 24-bit data of the most significant part (hereinafter, referred to as MSP) and 24-bit data of the least significant part (hereinafter, referred to as LSP). The MSP data of the multiple-precision data to be shifted is stored in the register 170, while the LSP data thereof is stored in the register 171. Also, it is assumed that MSP data of the result of the double-precision shift operation is stored in the register 170, while LSP data thereof is stored in the register 172.
The shift N-bit leftward double-precision shift operation is executed as shown in FIG. 10.
(1) The shift count "N" is stored in the register 110.
(2) LSP data stored in the register 171 is input into the shifter 120 as data (A). The shifter 120 shifts the LSP data leftward by N bit(s). The ALU 160 outputs the output of the shifter 120 (data (D)) without processing (through-output), which is stored in the register 172 as LSP data.
(3) The shift count "-(24-N)" is stored in the register 111.
(4) LSP data stored in the register 171 is input into the shifter 120 as data (A). The shifter 120 shifts the LSP data rightward by (24-N) bit(s). The ALU 160 outputs the output of the shifter 120 (data (D)) without processing (through-output), which is stored in the register 171.
(5) MSP data stored in the register 170 is input into the shifter 120 as data (A). The shifter 120 shifts the MSP data leftward by N bit(s). The data stored in the register 171 is input into the ALU 160 as data (E). The ALU 160 executes OR operation of the output of the shifter 120 (data (D)) and the data (E). The output of the ALU 160 is stored in the register 170 as MSP data.
The above N-bit leftward double-precision shift operation requires three shiftings excluding the setting of the shift counts. When the setting of the shift counts is included, the total number of operations required for the double-precision shift operation is greater. On the contrary, other double-precision operations (double-precision addition, double-precision subtraction, etc.) only require about two operations, indicating that the double-precision shift operation is, in general, significantly inefficient compared with other multiple-precision operations.
LD-CELP (low-delay CELP), one of the CELP type voice CODECs, has the advantage of having low delay, and thus has attracted attention as a CODEC for communication by wire (ISDN, etc.). In LD-CELP, the short-term prediction analysis processing occupies a large portion of the entire processing thereof compared with other CODECs. As a result, double-precision operations of as many as about 500 thousand times/sec. are required. This is about 25 times the number of double-precision operations executed in voice CODECs used for portable digital telephones, such as VSELP (vector sum excited linear prediction) and PSI-SELP (pitch synchronous innovation CELP). Accordingly, in realizing LD-CELP, it is essential to improve the efficiency of the double-precision shift operation.